1. Field of the Invention
The present invention relates to a method for fabricating a hybrid orientation substrate, and more particularly, to a method for fabricating a hybrid orientation substrate with solid phase epitaxy (SPE) technique.
2. Description of the Prior Art
Semiconductor device technology is increasingly relying on specialty Si-based substrates to improve the performance of complementary metal oxide semiconductor (CMOS) devices. For example, to fully take advantage of the silicon orientation dependence of carrier mobility, NMOS and PMOS transistors are respectively fabricated on (100)-Si substrate in which electron mobility is higher and on (110)-Si substrate in which hole mobility is higher. Such strong dependence of carrier mobility on silicon orientation has led to increased interest in the hybrid orientation substrate.
In prior art, the hybrid orientation substrate was achieved on direct silicon bonding (DSB) mixed orientation substrates using solid phase epitaxy (SPE). Please refer to FIGS. 1-5, which are schematic drawings illustrating a conventional method for fabricating a hybrid orientation substrate. As shown in FIG. 1, a (100)-oriented Si substrate 100 is provided and a (110)-oriented Si substrate 102 is directly bonded to the (100)-oriented Si substrate 100 by DSB technique without interfacial oxide formed in between. And a photoresist 104 is formed on the (110)-oriented Si substrate 102 to define an NMOS region 110 and a PMOS region 112.
Please refer to FIGS. 2-4. Then, a SPE method is used to convert the orientation of NMOS region 110 from (110)-oriented into (100)-oriented. As shown in FIG. 2, the NMOS region 110 is exposed to an amorphizing ion implantation 120 and is amorphized to a depth beyond the bonded interface between the (100)-oriented Si substrate 100 and the (110)-oriented Si substrate 102, thus an amorphized region 122 is formed.
Please refer to FIGS. 3 and 4. The amorphized region 122 is then recrystallized into the bottom crystal orientation. By using the (100)-oriented Si substrate 100 as a template, a (100)-oriented epitaxial region 124 is formed, and thus a hybrid orientation Si substrate is obtained. The interface region 130 between the (100)-oriented epitaxial region 124 and the (110)-oriented Si substrate is removed to form a shallow trench isolation (STI) 140 for providing an electrical isolation between the NMOS region 110 and the PMOS region 112 as shown in FIG. 5.
Please refer to FIG. 3 again. It is noteworthy that the (100)-oriented epitaxial region 124 is recrystallized along both surfaces of the (100)-oriented Si substrate 100 and the (110)-oriented Si substrate 102, respectively with the (100) and (110) crystalline orientations as the arrows shown in FIG. 3. Therefore the interface region 130 between the (100)-oriented epitaxial region 124 and the (110)-oriented Si substrate 102 is slanted as shown in FIG. 4. It is easily realized that the more slanted interface causes the bigger interface region 130. Since the slanted interface region 130 is entirely removed to form the STI 140, the bigger interface region 130 results the bigger STI 140 which consumes valuable space on a semiconductor wafer and reduces the integration of the semiconductor wafer.